The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Aug. 27, 2004
Neil G. Jacobson, Los Altos, CA (US);
Emigdio M. Flores, Jr., Coral Springs, FL (US);
Sanjay Srivastava, San Jose, CA (US);
Bin Dai, Mountain View, CA (US);
Sungnien Mao, Fremont, CA (US);
Rosa M. Y. Chow, Redwood City, CA (US);
Pushpasheel Tawade, San Jose, CA (US);
Neil G. Jacobson, Los Altos, CA (US);
Emigdio M. Flores, Jr., Coral Springs, FL (US);
Sanjay Srivastava, San Jose, CA (US);
Bin Dai, Mountain View, CA (US);
Sungnien Mao, Fremont, CA (US);
Rosa M. Y. Chow, Redwood City, CA (US);
Pushpasheel Tawade, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A bitstream having a plurality of data sets is provided to an integrated circuit device such as an FPGA having test circuitry capable of routing data to the device's internal resources, with each data set including configuration information and a trigger signal. Successive data sets of the bitstream are sequentially processed by the test circuitry in response to the trigger signals to sequentially initialize the device's resources to various states. For some embodiments, each data set includes configuration data to configure one or more configurable elements of the device to implement a desired design and includes soft data for use by a processor embedded within the device. For one embodiment, control logic is provided to selectively wait for a predetermined time period before processing a next data set.