The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2007

Filed:

Jan. 29, 2003
Applicants:

Rabin A. Sugumar, Sunnyvale, CA (US);

Sorin Iacobovici, San Jose, CA (US);

Robert Nuckolls, Sunnyvale, CA (US);

Chandra M. R. Thimmannagari, Fremont, CA (US);

Inventors:

Rabin A. Sugumar, Sunnyvale, CA (US);

Sorin Iacobovici, San Jose, CA (US);

Robert Nuckolls, Sunnyvale, CA (US);

Chandra M. R. Thimmannagari, Fremont, CA (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 9/40 (2006.01); G06F 15/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.


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