Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain

Abstract

A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (S(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.