The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Feb. 15, 2005
Michio Nakagawa, Kyoto, JP;
Kazuo Sato, Kyoto, JP;
Hiromi Uenoyama, Kyoto, JP;
Yasuyuki Ohnishi, Kyoto, JP;
Kazunori Torii, Kyoto, JP;
Michio Nakagawa, Kyoto, JP;
Kazuo Sato, Kyoto, JP;
Hiromi Uenoyama, Kyoto, JP;
Yasuyuki Ohnishi, Kyoto, JP;
Kazunori Torii, Kyoto, JP;
Rohm Co., Ltd., Kyoto, JP;
Abstract
A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.