The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Oct. 29, 2003
Franklin Duan, San Jose, CA (US);
Minxuan Liu, San Jose, CA (US);
John Walker, Colorado Springs, CO (US);
Nabil Monsour, Colorado Springs, CO (US);
Carl Monzel, Eagan, MN (US);
Franklin Duan, San Jose, CA (US);
Minxuan Liu, San Jose, CA (US);
John Walker, Colorado Springs, CO (US);
Nabil Monsour, Colorado Springs, CO (US);
Carl Monzel, Eagan, MN (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A test methodology which provides that test structures, such as transistors, are arranged in a plurality of rows. A logic circuit controls which row is to be measured. An incrementer receives a triggering signal and functions as an address adder. Each time the triggering signal rises from 0 to 1, the output of the incrementer increases by 1. The output of the incrementer serves as the address input into a decoder. The decoder is connected to the rows of test structures. Preferably, each test structure contains a control circuit which is controlled by this signal (i.e., the output of the decoder). If the test structures are transistors, bias to each of the transistors can be applied separately with a common gate, source and well, and measurement can be done with a separate drain node.