The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7189962 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 13, 2007

Filed:

Feb. 17, 2005
Applicant:

Taizo Tomioka, Yokohama, JP;

Inventor:

Taizo Tomioka, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01J 40/14 (2006.01); H03K 17/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

Three chips, i.e., an LED, photovoltaic IC, and MOS-FET, are mounted on a silicon substrate having two projections arranged substantially parallel to each other. Each projection has a side surface formed by an inclined surface including a curve having an inflection point. The LED is mounted on an LED mounting electrode formed between the two projections, and connected, by a gold wire, to an LED connecting electrode formed between the projections. The photovoltaic IC is placed on the front-side surfaces of the projections so as to oppose the LED, and connected via gold bumps.


Find Patent Forward Citations

Tomioka, Taizo. (2007). Semiconductor relay apparatus and wiring board fabrication method (U.S. Patent No. 7189962). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7189962

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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