The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7189621 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 13, 2007

Filed:

Nov. 12, 2004
Applicants:

Hiroshi Inagawa, Maebashi, JP;

Nobuo Machida, Takasaki, JP;

Kentaro Ooishi, Takasaki, JP;

Inventors:

Hiroshi Inagawa, Maebashi, JP;

Nobuo Machida, Takasaki, JP;

Kentaro Ooishi, Takasaki, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. In this method, a trench wherein a trench-gate is to be formed is formed on the main surface of the semiconductor substrate with the insulating film formed thereon with a mask; and the side surface of the insulating film is caused to retreat from the upper end of the trench by isotropic etching, whereby a gate insulating film and a conductive layer to be the trench gate are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench. According to the present invention, occurrence of a source offset and damage of a gate insulating film can be prevented.


Find Patent Forward Citations

Inagawa, Hiroshi. (2007). Semiconductor device and method for fabricating the same (U.S. Patent No. 7189621). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7189621

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