The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Jan. 18, 2005
Satyavolu Srinivas Papa Rao, Garland, TX (US);
Darius Lammont Crenshaw, Allen, TX (US);
Stephan Grunow, Dallas, TX (US);
Kenneth D. Brennan, Plano, TX (US);
Somit Joshi, Sunnyvale, CA (US);
Montray Leavy, McKinney, TX (US);
Phillip D. Matz, McKinney, TX (US);
Sameer Kumar Ajmera, Richardson, TX (US);
Yuri E. Solomentsev, Austin, TX (US);
Satyavolu Srinivas Papa Rao, Garland, TX (US);
Darius Lammont Crenshaw, Allen, TX (US);
Stephan Grunow, Dallas, TX (US);
Kenneth D. Brennan, Plano, TX (US);
Somit Joshi, Sunnyvale, CA (US);
Montray Leavy, McKinney, TX (US);
Phillip D. Matz, McKinney, TX (US);
Sameer Kumar Ajmera, Richardson, TX (US);
Yuri E. Solomentsev, Austin, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The formation of a MIM (metal insulator metal) capacitor () and concurrent formation of a resistor () is disclosed. A copper diffusion barrier () is formed over a copper deposition () that serves as a bottom electrode () of the capacitor (). The copper diffusion barrier () mitigates unwanted diffusion of copper from the copper deposition (), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface () of the deposition of copper/bottom electrode. Subsequently, layers of dielectric () and conductive () materials are applied to form a dielectric () and top electrode () of the MIM capacitor (), respectively, where the layer of conductive top electrode material () also functions to concurrently develop the resistor () on the same chip as the capacitor ().