The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Sep. 10, 2004
Vaidyanathan Kripesh, Singapore, SG;
Wai Kwan Wong, Singapore, SG;
Mihai Dragos Rotaru, Singapore, SG;
Tai Chong Chai, Singapore, SG;
Mahadevan Krishna Iyer, Singapore, SG;
Vaidyanathan Kripesh, Singapore, SG;
Wai Kwan Wong, Singapore, SG;
Mihai Dragos Rotaru, Singapore, SG;
Tai Chong Chai, Singapore, SG;
Mahadevan Krishna Iyer, Singapore, SG;
Agency for Science, Technology and Research, Singapore, SG;
Abstract
A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.