The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2007

Filed:

Dec. 16, 2003
Applicants:

Glen Phillip Carey, Palo Alto, CA (US);

Ian Jenks, Northhamptonshire, GB;

Alan Lewis, Sunnyvale, CA (US);

René Lujan, Sunnyvale, CA (US);

Hailong Zhou, Milpitas, CA (US);

Jacy R. Titus, San Jose, CA (US);

Gideon W. Yoffe, Fremont, CA (US);

Mark A. Emanuel, Morgan Hill, CA (US);

Aram Mooradian, Kentfield, CA (US);

Inventors:

Glen Phillip Carey, Palo Alto, CA (US);

Ian Jenks, Northhamptonshire, GB;

Alan Lewis, Sunnyvale, CA (US);

René Lujan, Sunnyvale, CA (US);

Hailong Zhou, Milpitas, CA (US);

Jacy R. Titus, San Jose, CA (US);

Gideon W. Yoffe, Fremont, CA (US);

Mark A. Emanuel, Morgan Hill, CA (US);

Aram Mooradian, Kentfield, CA (US);

Assignee:

Novalux, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a semiconductor device is described. In this method, a starting substrate of sufficient thickness is selected that has the required defect density levels, which may result in an undesirable doping level. Then a semiconductor layer having a desired doping level is formed on the starting substrate. The resulting semiconductor layer has the required defect density and doping levels for the final product application. After active components, electrical conductors, and any other needed structures are formed on the semiconductor layer, the starting substrate is removed leaving a desired thickness of the semiconductor layer. In a VECSEL application, the active components can be a gain cavity, where the semiconductor layer has the necessary defect density and doping levels to maximize wall plug efficiency (WPE). In one embodiment, the doping of the semiconductor layer is not uniform. For example, a majority of the layer is doped at a low level and the remainder is doped at a much higher level. This can result in improved WPE at particular thicknesses for the higher doped material.


Find Patent Forward Citations

Loading…