The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7185295 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 27, 2007

Filed:

Jun. 01, 2001
Applicants:

Hyunju Park, Seoul 130-083, KR;

Dong Goo Yun, Seoul, KR;

Inventors:

Hyunju Park, Seoul 130-083, KR;

Dong Goo Yun, Seoul, KR;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

A chip design verifying and chip testing apparatus is provided including a storing means for storing an application program verifying an operation of a chip and testing the chip, the chip having a plurality of blocks, an I/O file, and a test vector; an interface means controlling a data transmission between the storing means and the chip, the interface means having a data applying means for applying the I/O file and/or the test vector outputted from the storing means and a data storing means for storing data outputted from the chip; and a computer including a CPU for performing and controlling the application program.


Find Patent Forward Citations

Park, Hyunju. (2007). Chip design verifying and chip testing apparatus and method (U.S. Patent No. 7185295). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7185295

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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