On-chip timing characterizer

Abstract

An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits providing increased accuracy and range. The measurement circuit includes a chip delay element characterization circuit for determining chip specific delay values having one output connected to a second control input of the programmable delay generator and receiving an output from the programmable delay generator for providing a value corresponding to the measured chip specific delay element timing, the characterization circuit being enabled by a control signal from the analyzer during a setup phase of the measurement cycle thereby enhancing the accuracy of the measurement for both skew measurement and timing parameter characterization.