The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2007

Filed:

Dec. 10, 2003
Applicants:

William Fredenburg, Apex, NC (US);

Kenneth Michael Key, Raleigh, NC (US);

Michael L. Wright, Raleigh, NC (US);

John William Marshall, Cary, NC (US);

Inventors:

William Fredenburg, Apex, NC (US);

Kenneth Michael Key, Raleigh, NC (US);

Michael L. Wright, Raleigh, NC (US);

John William Marshall, Cary, NC (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.


Find Patent Forward Citations

Fredenburg, William. (2007). Processor isolation technique for integrated multi-processor systems (U.S. Patent No. 7185224). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7185224

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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