The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2007

Filed:

Dec. 27, 2001
Applicant:

Shinji Saito, Kasugai, JP;

Inventor:

Shinji Saito, Kasugai, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A PLL frequency synthesizer suitable for improving even a spurious characteristic in a lock state while ensuring a high-speed lockup characteristic to thereby implement satisfactoy communication quality includes a switch circuit interposed between a low-pass filter circuit and a voltage-controlled oscillator controlled based on a control signal to open/close control a feedback loop lying between the low-pass filter circuit and the voltage-controlled oscillator. The switch circuit is opened according to a path-opening instruction of a feedback loop based on the control signal to open the feedback loop, thereby stopping the operation of the feedback loop. If this stop operation is controlled according to the control signal so as to he carried out during a period in which a pseudo correction pulse is outputted from a charge pump circuit for each phase comparison cycle of a phase comparator, then spurious generation incident to the pseudo correction pulse can be suppressed.


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