The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2007
Filed:
Apr. 06, 2004
Milind P. Padhye, Austin, TX (US);
Christopher K. Y. Chun, Austin, TX (US);
Yuan Yuan, Austin, TX (US);
Sanjay Gupta, Delhi, IN;
Milind P. Padhye, Austin, TX (US);
Christopher K. Y. Chun, Austin, TX (US);
Yuan Yuan, Austin, TX (US);
Sanjay Gupta, Delhi, IN;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.