The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2007

Filed:

Sep. 26, 2005
Applicants:

Kwang-il Park, Yongin-si, KR;

Hyun-dong Kim, Seoul, KR;

Mi-jin Lee, Suwon-si, KR;

Inventors:

Kwang-Il Park, Yongin-si, KR;

Hyun-Dong Kim, Seoul, KR;

Mi-Jin Lee, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/017 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a duty cycle correction circuit and method for duty cycle correction in a delay locked loop using an inversion locking scheme. The duty cycle correction circuit comprises: a correction unit exchanging and receiving a first duty correction signal and a second duty correction signal and selecting and receiving one of an input clock signal and an inversion signal of the input clock signal in response to an inversion locking signal, and correcting the duty cycle of the received input clock signal or inversion signal of the input clock signal in response to the first and second duty correction signals; a buffer buffering an output signal of the correction unit and outputting the buffered signal as a corrected clock signal; and a duty detector selecting and receiving one of the corrected clock signal and an inversion signal of the corrected clock signal in response to the inversion locking signal, and generating the first and second duty correction signals using the received corrected clock signal or inversion signal of the corrected clock signal.


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