Programmable logic auto write-back

Abstract

A first configuration controller loads configuration data into a programmable logic device. The first controller is coupled with a first configuration memory and manages couplings of the memory to a first load path. The load path couples to a latch ring, which receives configuration data from the first memory. An array of configuration latches receives the configuration from the latch ring and effects a configuration of the programmable device. A write-back path couples the latch ring and first configuration memory. A write-back controller manages write-back operations of configuration data from the latch ring to the configuration memory. A second configuration controller is coupled to a second configuration memory, which is coupled to a second load path. The second controller and second memory operate like the first. The write-back controller can be configured to couple to the second memory and facilitate development processes by a writing-back developmental configurations.