The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2007
Filed:
Feb. 10, 2005
Elianne A. Bravo, Wappingers Falls, NY (US);
Kenneth Y. Chan, Hopewell Junction, NY (US);
Kevin C. Gower, LaGrangeville, NY (US);
Dustin J. Vanstee, Poughkeepsie, NY (US);
Elianne A. Bravo, Wappingers Falls, NY (US);
Kenneth Y. Chan, Hopewell Junction, NY (US);
Kevin C. Gower, LaGrangeville, NY (US);
Dustin J. VanStee, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.