The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2007
Filed:
Mar. 22, 2001
Mark Tuomenoksa, Winchester, MA (US);
Samuel Bendinelli, Princeton, NJ (US);
Jerold Francus, Far Hills, NJ (US);
Jonathan Harwood, Rumson, NJ (US);
Michael Herrick, Colts Neck, NJ (US);
John Keane, Metuchen, NJ (US);
Christopher Macey, Red Bank, NJ (US);
Brion Shimamoto, Riverside, CT (US);
Mark Tuomenoksa, Winchester, MA (US);
Samuel Bendinelli, Princeton, NJ (US);
Jerold Francus, Far Hills, NJ (US);
Jonathan Harwood, Rumson, NJ (US);
Michael Herrick, Colts Neck, NJ (US);
John Keane, Metuchen, NJ (US);
Christopher Macey, Red Bank, NJ (US);
Brion Shimamoto, Riverside, CT (US);
Corente, Inc., East Brunswick, NJ (US);
Abstract
Methods and systems are provided for enabling a network between a first and a second processor using at least one additional processor separate from the first and second processors. In one embodiment, the at least one additional processor receives information indicating a consent on behalf of the first processor to enabling a tunnel between the first processor and the second processor and receives information indicating a consent on behalf of the second processor to enabling a tunnel between the second processor and the first processor. The at least one additional processor determines a first virtual address for the first processor and a second virtual address for the second processor such that the first and second virtual addresses uniquely identify the first and second processors, respectively, and are routable through the network. The at least one additional processor provides to each of the first and second processors the first and second virtual addresses to enable one or more tunnels between the first and the second processors.