The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2007
Filed:
Oct. 04, 2005
Applicant:
Ghasi R. Agrawal, Cupertino, CA (US);
Inventor:
Ghasi R. Agrawal, Cupertino, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A circuit is configured as a splittable duplex memory cell or as a joinable single port memory pair based on the state of a programming layer. The programming layer has two states. In one state, the programming layer configures the circuit as a joinable single port memory pair. In the other state it configures the circuit as a splittable duplex memory cell. As such, the circuit can act as either a dual port memory cell or as two single port memory cells.