The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2007
Filed:
Feb. 28, 2003
Applicants:
Ankur Bal, Ghaziabad, IN;
Manish Agarwal, Lucknow, IN;
Inventors:
Ankur Bal, Ghaziabad, IN;
Manish Agarwal, Lucknow, IN;
Assignee:
STMicroelectronics Pvt. Ltd., , IN;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
Abstract
An efficient method and electronic circuit for initializing latch arrays in an electronic device including an FPGA and a memory device includes a group of one or more data latches, each including a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring significant additional circuitry.
Bal, Ankur. (2007). Efficient latch array initialization (U.S. Patent No. 7180792). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7180792
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile