The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2007
Filed:
Jan. 03, 2005
Vincent Gosmain, Aix-en-Provence, FR;
David Bernard, Aix-en-Provence, FR;
Vincent Gosmain, Aix-en-Provence, FR;
David Bernard, Aix-en-Provence, FR;
Atmel Corporation, San Jose, CA (US);
Abstract
An input/output (I/O) buffer having an input mode and coupled between first and second supply voltages includes a PMOS pull-up transistor fabricated in an nwell, and a gate bias control transistor coupled to the gate of the PMOS pull-up transistor for coupling the gate of the PMOS pull-up transistor to an input/output node in response to an input signal having a voltage greater than approximately the first supply voltage. A well bias control circuit is coupled to the PMOS pull-up transistor and to a well drive transistor to couple the nwell terminal to the first supply voltage in response to the input signal having a voltage approximately equal to or less than the first supply voltage.