The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2007

Filed:

Apr. 21, 2005
Applicants:

Andy C. Wei, Radebeul/Dresden, DE;

Derick J. Wristers, Bee Caves, TX (US);

Mark B. Fuselier, Austin, TX (US);

Inventors:

Andy C. Wei, Radebeul/Dresden, DE;

Derick J. Wristers, Bee Caves, TX (US);

Mark B. Fuselier, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/01 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one illustrative embodiment, the device comprises a transistor formed above a silicon-on-insulator substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the bulk substrate being doped with a first type of dopant material and a first well formed in the bulk substrate, the first well being doped with a second type of dopant material that is of a type opposite the first type of dopant material. The device further comprises a second well formed in the bulk substrate within the first well, the second well being doped with a dopant material that is the same type as the first type of dopant material, the transistor being formed in the active layer above the second well, an electrical contact for the first well and an electrical contact for said second well. In one illustrative embodiment, a method of forming a transistor above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the bulk substrate being doped with a first type of dopant material is disclosed. The method comprises performing a first ion implant process using a dopant material that is of a type opposite the first type of dopant material to form a first well region within the bulk substrate, performing a second ion implant process using a dopant material that is the same type as the first type of dopant material to form a second well region in the bulk substrate within the first well, the transistor being formed in the active layer above the second well, forming a conductive contact to the first well and forming a conductive contact to the second well. The method further comprises a contact well formed in the bulk substrate within the first well, the contact well being comprised of a dopant material that is of the same type as the second type of dopant material, the contact well within the first well having a dopant concentration that is greater than a dopant concentration of the first well.


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