The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2007
Filed:
Sep. 29, 2004
Applicants:
Dimitris E. Ioannou, Fairfax, VA (US);
Souvick Mitra, Burlington, VT (US);
Akram Salman, Sunnyvale, CA (US);
Inventors:
Dimitris E. Ioannou, Fairfax, VA (US);
Souvick Mitra, Burlington, VT (US);
Akram Salman, Sunnyvale, CA (US);
Assignee:
George Mason Intellectual Properties, Inc., Fairfax, VA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/01 (2006.01);
U.S. Cl.
CPC ...
Abstract
Disclosed is a Silicon-On-Insulator (SOI) Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) logic family composed of ratioed logic with intrinsically 'on' symmetric fully depleted double-gate (DG) SOI MOSFET load(s) and asymmetric fully depleted double gate MOSFET driver(s).
Ioannou, Dimitris. (2007). Double gate (dg) soi ratioed logic with intrinsically on symmetric dg-mosfet load (U.S. Patent No. 7180135). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7180135
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile