The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2007

Filed:

Jul. 11, 2003
Applicants:

Sung-kwon Lee, Ichon-shi, KR;

Min-suk Lee, Ichon-shi, KR;

Sang-ik Kim, Ichon-shi, KR;

Inventors:

Sung-Kwon Lee, Ichon-shi, KR;

Min-Suk Lee, Ichon-shi, KR;

Sang-Ik Kim, Ichon-shi, KR;

Assignee:

Hynix Semiconductor Inc., Kyoungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); C09K 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a semiconductor device includes the steps of: (a) forming a plurality of conductive patterns on a substrate in a cell region and a peripheral circuit region; (b) forming an insulation layer on an entire surface of the resulting structure from the step. (a); (c) forming a plurality of plugs in the cell region and simultaneously forming a dummy pattern in a region between the cell region and the peripheral circuit region, each plug and the dummy pattern being contacted to the substrate allocated between the conductive patterns by passing through the insulation layer; (d) forming a photoresist pattern masking the resulting structure in the cell region; and (e) removing the insulation layer in the peripheral circuit region by performing a wet etching process with use of the photoresist pattern as an etch mask to thereby expose a surface of the substrate in the peripheral circuit region.


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