The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7178124 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 13, 2007

Filed:

May. 30, 2003
Applicants:

Mikhail Makarov, Moscow, RU;

Igor Chourkin, Moscow, RU;

Mikhail Komarov, Moscow, RU;

Boris Ginzburg, Santa Clara, CA (US);

Inventors:

Mikhail Makarov, Moscow, RU;

Igor Chourkin, Moscow, RU;

Mikhail Komarov, Moscow, RU;

Boris Ginzburg, Santa Clara, CA (US);

Assignee:

Golden Gate Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, algorithm, software, architecture and system for placing circuit components and routing wires. The method and algorithm generally include (a) placing components in an array of allowed locations, wherein each of the components receives a clock signal and each of the allowed locations is about the same distance from a first nearest neighbor along at least a first axis as are other allowed locations along said first axis, and (b) one of the following: (i) independently routing a plurality of combinational paths from at least two components to at least two other components, (ii) routing the clock signal to the components, or both (i) and (ii). The present method, algorithm, software, architecture and system advantageously reduce power and/or current consumption in integrated circuits, improve uniformity of timing for signal paths between clocked circuit components, and/or ensure that timing requirements for signal paths between clocked circuit components are met automatically.


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