The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2007

Filed:

Mar. 16, 2005
Applicants:

Bum-ki Baek, Suwon, KR;

Mun-pyo Hong, Seongnam, KR;

Jang-soo Kim, Suwon, KR;

Sung-wook Hao, Seoul, KR;

Jong-soo Yoon, Cheonan, KR;

Dong-gyu Kim, Suwon, KR;

Inventors:

Bum-Ki Baek, Suwon, KR;

Mun-Pyo Hong, Seongnam, KR;

Jang-Soo Kim, Suwon, KR;

Sung-Wook Hao, Seoul, KR;

Jong-Soo Yoon, Cheonan, KR;

Dong-Gyu Kim, Suwon, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 29/15 (2006.01); H01L 31/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.


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