The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2007

Filed:

Nov. 18, 2004
Applicants:

James D. Chlipala, Lower Macungie Township, Lehigh County, PA (US);

Shahriar Moinian, New Providence, NJ (US);

Inventors:

James D. Chlipala, Lower Macungie Township, Lehigh County, PA (US);

Shahriar Moinian, New Providence, NJ (US);

Assignee:

Agere Systems, Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an optical proximity effect of a second semiconductor device, selecting a modeling design parameter such that the isolation structure stress effect is offset against the optical proximity effect on a fabrication model, and using the selected design parameter to construct a third semiconductor device.


Find Patent Forward Citations

Chlipala, James. (2007). Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects (U.S. Patent No. 7174532). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7174532

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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