The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7173464 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 06, 2007

Filed:

Feb. 16, 2005
Applicant:

Makoto Nagasue, Tokyo, JP;

Inventor:

Makoto Nagasue, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 7/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a duty adjustment circuit, a clock signal is frequency-divided to ½by a frequency divider. In a first frequency doubler among n cascade-connected frequency doublers, the divided clock signal is delayed by a variable delay portion according to a control signal. The exclusive logical sum of the delayed signal and the divided clock signal in the frequency-doubling portion doubles the frequency. The average voltage of the frequency-doubled signal is detected by an average value detection portion, and is compared with a reference voltage by a comparison control portion. A control signal is fed back to the variable delay portion to cause the average voltage to become equal to the reference voltage. In this manner, a clock signal is generated from the last frequency doubler with frequency equal to that of the original clock signal, and with duty ratio adjusted to a desired value.


Find Patent Forward Citations

Nagasue, Makoto. (2007). Duty adjustment circuit (U.S. Patent No. 7173464). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7173464

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