The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 2007
Filed:
May. 18, 2005
Oleg Siniaguine, San Carlos, CA (US);
Oleg Siniaguine, San Carlos, CA (US);
Tru-Si Technologies, Inc., Sunnyvale, CA (US);
Abstract
A clock distribution network () is formed on a semiconductor interposer () which is a semiconductor integrated circuit. An input terminal () of the clock distribution network is formed on one side of the interposer, and output terminals () of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals () is bonded to a second integrated circuit () containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (). The interposer contains a ground structure, or ground structures (), that shield circuitry from the clock distribution network. Conductive lines () in an integrated circuit are formed in trenches () in a semiconductor substrate.