The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7172925 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 06, 2007

Filed:

Dec. 12, 2002
Applicant:

Keiichi Murakami, Komaki, JP;

Inventor:

Keiichi Murakami, Komaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H05K 7/02 (2006.01); B05D 5/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a method for manufacturing a flat printed wiring board in which spaces between circuit patterns are filled with a resin. The method comprises: laminating via a mold release film a plurality of sets of laminated bodies formed by superposing a semi-cured resin sheet on a printed wiring board with circuit patterns formed thereon; placing the laminated plural sets of the laminated bodies interposed between a pair of smoothing plates and collectively pressing the laminated bodies in a reduced pressure atmosphere used for curing the resin; and then polishing the cured resin covering the circuit patterns, thereby exposing the circuit patterns.


Find Patent Forward Citations

Murakami, Keiichi. (2007). Method for manufacturing printed wiring board (U.S. Patent No. 7172925). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7172925

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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