The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7171641 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 30, 2007

Filed:

Jan. 17, 2003
Applicants:

Shinichi Kurose, Kawasaki, JP;

Seiji Goto, Kawasaki, JP;

Inventors:

Shinichi Kurose, Kawasaki, JP;

Seiji Goto, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for designing a semiconductor integrated circuit is proposed. The semiconductor integrated circuit includes power supply terminals each formed out of an area bump and signal terminals. Distance from the logic cell or the module to a power supply area bump closest thereto is obtained for the logic cell or the module. Further, a power supply voltage which is estimated to be actually applied to the logic cell or the module is obtained based on the obtained distance and a power supply voltage applied to the power supply area bump. Finally, a delay is calculated based on the estimated power supply voltage.


Find Patent Forward Citations

Kurose, Shinichi. (2007). Voltage change reflecting delay calculation method, and voltage change reflecting delay calculation system (U.S. Patent No. 7171641). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7171641

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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