The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2007
Filed:
Oct. 06, 2003
Hugo Cheung, Tucson, AZ (US);
Herbert Braisz, Marana, AZ (US);
Hugo Cheung, Tucson, AZ (US);
Herbert Braisz, Marana, AZ (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively operates in a normal mode and one or more divide modes, wherein the divide modes provide a clock frequency that is a fraction of the normal clock frequency by a divisor value that is specified in a user-accessible divider register. Lower divisor values (e.g., 2, 4, 8, etc.) are preferably used for performance tuning, while large divisor values (e.g., 1024, 2048, and 4096) are preferably used for power saving.