The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2007
Filed:
Jun. 19, 2001
Donald E. Alfano, Round Rock, TX (US);
Danny Allred, Austin, TX (US);
Douglas S. Piasecki, Austin, TX (US);
Kenneth W. Fernald, Austin, TX (US);
Ka Y Leung, Austin, TX (US);
Brian Caloway, Georgetown, TX (US);
Alvin Storvik, Austin, TX (US);
Paul Highley, Austin, TX (US);
Douglas R Holberg, Wimberley, TX (US);
Donald E. Alfano, Round Rock, TX (US);
Danny Allred, Austin, TX (US);
Douglas S. Piasecki, Austin, TX (US);
Kenneth W. Fernald, Austin, TX (US);
Ka Y Leung, Austin, TX (US);
Brian Caloway, Georgetown, TX (US);
Alvin Storvik, Austin, TX (US);
Paul Highley, Austin, TX (US);
Douglas R Holberg, Wimberley, TX (US);
Silicon Labs CP, Inc., Austin, TX (US);
Abstract
A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.