Integrated semiconductor memory device for synchronizing a signal with a clock signal

Abstract

A semiconductor memory includes a control circuit for generating an internal read command signal depending on an externally applied read command signal. A clock generating circuit generates a system clock signal and a time shifted clock signal generated by a DLL circuit. A latency counter circuit comprises a first control circuit for generating a first control signal and a second control circuit for generating a second control signal. The first control signal is used to latch the internal read command signal in one of FIFO-latching cells. The latching is carried out in a system clock domain. The second control signal is used to release a time shifted internal read command signal from one of the FIFO-latching cells in a DLL clock domain. The relationship between first and second control signals determines a CAS latency by which data items appear at a data terminal synchronous with an externally applied clock signal.