The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2007
Filed:
May. 19, 2004
Yasuaki Iwase, Tenri, JP;
Yoshifumi Yaoi, Yamatokoriyama, JP;
Hiroshi Iwata, Nara, JP;
Akihide Shibata, Nara, JP;
Yoshinao Morikawa, Ikoma, JP;
Masaru Nawaki, Nara, JP;
Yasuaki Iwase, Tenri, JP;
Yoshifumi Yaoi, Yamatokoriyama, JP;
Hiroshi Iwata, Nara, JP;
Akihide Shibata, Nara, JP;
Yoshinao Morikawa, Ikoma, JP;
Masaru Nawaki, Nara, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A programming verification method of verifying programming of a nonvolatile memory cell, the method comprising at least the steps of: selecting first, second, . . . and n-th references corresponding to first, second, . . . and n-th threshold voltages specifying lower limit values of states, . . . and n, respectively; applying a programming voltage to the nonvolatile memory cell; sensing a threshold voltage level of the nonvolatile memory cell; comparing the sensed threshold voltage level with the first reference to output a first result; comparing the threshold voltage level with one of the second and third references selected according to the first result to output a second result; and comparing the first and second results with an expectation value and, in the case where the first and second results are equal to the expectation value, indicating that the programming has succeeded, wherein the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, a source and a drain as diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.