The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2007
Filed:
Mar. 17, 2005
Hiroaki Yabu, Kyoto, JP;
Hiroaki Yabu, Kyoto, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A semiconductor integrated circuit of the present invention includes, between a power lineand a ground line, an NMIS transistorcapable of supplying fixed signals with low and high levels to the outside, an NMIS transistorhaving a source connected to a gate of the NMIS transistor, a PMIS transistorhaving a drain connected to a gate of the NMIS transistor, and an ESD protection power clamp circuit. If a surge is applied to the power line, the ESD protection power clamp circuitis clamped to pass the surge to the ground line. While the surge is passed, the potential of the power linerises to turn on the three transistors, and. At this time, the NMIS transistorand the PMIS transistorcan reduce the gate potential of the NMIS transistorlower than the potential of the power line