The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2007

Filed:

Oct. 05, 2001
Applicants:

Shinya Tokunaga, Kyoto, JP;

Shigeki Furuya, Osaka, JP;

Yuuji Hinatsu, Kyoto, JP;

Inventors:

Shinya Tokunaga, Kyoto, JP;

Shigeki Furuya, Osaka, JP;

Yuuji Hinatsu, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 29/739 (2006.01); H01L 29/73 (2006.01); H01L 29/74 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.


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