The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2007

Filed:

Nov. 15, 2004
Applicants:

Omar Zia, Austin, TX (US);

Lawrence Cary Gunn, Iii, Encinitas, CA (US);

Inventors:

Omar Zia, Austin, TX (US);

Lawrence Cary Gunn, III, Encinitas, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate includes forming openings within an active semiconductor layer in first and second regions of a semiconductor substrate. The first region corresponds to a non-MOS transistor device portion and the second region corresponds to a CMOS electronic device portion. The openings are formed using a dual trench process, forming openings or shallow trenches in the non-MOS transistor device portion to a first depth, and openings in the CMOS electronic device portion to a second depth greater than the first depth. The method further includes forming first and second non-MOS transistor device implant regions within the active semiconductor layer underlying the shallow trenches in the non-MOS transistor device portion, forming first and second low dose non-MOS transistor device well regions in the active semiconductor layer disposed in-between the first and second shallow trenches, forming high dose non-MOS transistor device connectivity regions, forming a salicide blocking layer overlying at least the first and second low dose non-MOS transistor device well regions, forming first and second non-MOS transistor device contact regions, and saliciding the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the first and second low dose non-MOS transistor device well regions.


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