The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 23, 2007
Filed:
Jan. 28, 2003
Murphy Chen, Taipei, TW;
Perlman HU, Taipei, TW;
Murphy Chen, Taipei, TW;
Perlman Hu, Taipei, TW;
VIA Technologies, Inc., Shindian, TW;
Abstract
A method and a device for testing an embedded phase-locked loop (PLL) circuit are disclosed. A first clock signal of a first frequency is provided to an embedded phase-locked loop (PLL) circuit to be tested by a tester, so as to generate a PLL clock signal by the embedded PLL circuit in response to the first clock signal of the first frequency. The PLL clock signal is inputted to a test circuit along with a second clock signal of a second frequency. Then, the PLL clock signal is sampled with the second clock signal of the second frequency to generate a first sampled signal. The second frequency has a first correlation with the first frequency. Whether the embedded PLL circuit is in a normal operation condition is determined according to the first sampled signal.