The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2007

Filed:

Aug. 26, 2003
Applicants:

Sung-ryul Kim, Kyungki-do, KR;

Jong-bok Tcho, Kyungki-do, KR;

Woo-seop Jeong, Kyungki-do, KR;

Inventors:

Sung-ryul Kim, Kyungki-do, KR;

Jong-bok Tcho, Kyungki-do, KR;

Woo-seop Jeong, Kyungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory device, such as a DDR SDRAM, may be provided in which subsets of data output circuits of the device can be selectively enabled to allow sets of data output pins to be connected in common in a testing configuration. In some embodiments, a memory device includes a plurality of data output circuits, respective ones of which are configured to receive data from respective internal data lines and respective ones of which are coupled to respective data input/output pins. The device further includes a data output control circuit operative to selectively enable subsets of the plurality of data output circuits to drive their respective corresponding data input/output pins responsive to an externally-applied control signal. The data output control circuit may be operative to selectively cause subsets of the plurality of data output circuits to present a high impedance at their respective corresponding data input/output pins. The invention may be embodied as devices and methods.


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