The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2007

Filed:

Nov. 03, 2004
Applicants:

Jorge Salcedo-suner, Allen, TX (US);

Charvaka Duvvury, Plano, TX (US);

Roger A. Cline, Plano, TX (US);

Jose A. Cadena-hernandez, Wylie, TX (US);

Inventors:

Jorge Salcedo-Suner, Allen, TX (US);

Charvaka Duvvury, Plano, TX (US);

Roger A. Cline, Plano, TX (US);

Jose A. Cadena-Hernandez, Wylie, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard ring surrounding the diode device; a diode coupled between a second end of the string of diodes and an output pad; a second NWELL guard ring surrounding the diode; and a transistor device coupled between the output pad and a substrate node. The NWELL guardrings disrupt the parasitic SCR operation by adding an additional N+ diffusion without affecting the substrate pump current delivered by the diode.


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