The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 23, 2007
Filed:
Jun. 09, 2003
Jerome F. Duluk, Jr., Palo Alto, CA (US);
Richard E. Hessel, Pleasanton, CA (US);
Vaughn T. Arnold, Scotts Valley, CA (US);
Jack Benkual, Cupertino, CA (US);
Joseph P. Bratt, San Jose, CA (US);
George Cuan, Sunnyvale, CA (US);
Stephen L. Dodgen, Boulder Creek, CA (US);
Emerson S. Fang, Fremont, CA (US);
Zhaoyu Gong, Cupertino, CA (US);
Thomas Y. Ho, Fremont, CA (US);
Hengwei Hsu, Fremont, CA (US);
Sidong LI, San Jose, CA (US);
Sam NG, Fremont, CA (US);
Matthew N. Papakipos, Menlo Park, CA (US);
Jason R. Redgrave, Mountain View, CA (US);
Sushma S. Trivedi, Sunnyvale, CA (US);
Nathan D. Tuck, San Diego, CA (US);
Shun Wai Go, Milpitas, CA (US);
Lindy Fung, Sunnyvale, CA (US);
Tuan D. Nguyen, San Jose, CA (US);
Joseph P. Grass, Menlo Park, CA (US);
BO Hong, San Jose, CA (US);
Abraham Mammen, Pleasanton, CA (US);
Abbas Rashid, Fremont, CA (US);
Albert Suan-wei Tsay, Fremont, CA (US);
Jerome F. Duluk, Jr., Palo Alto, CA (US);
Richard E. Hessel, Pleasanton, CA (US);
Vaughn T. Arnold, Scotts Valley, CA (US);
Jack Benkual, Cupertino, CA (US);
Joseph P. Bratt, San Jose, CA (US);
George Cuan, Sunnyvale, CA (US);
Stephen L. Dodgen, Boulder Creek, CA (US);
Emerson S. Fang, Fremont, CA (US);
Zhaoyu Gong, Cupertino, CA (US);
Thomas Y. Ho, Fremont, CA (US);
Hengwei Hsu, Fremont, CA (US);
Sidong Li, San Jose, CA (US);
Sam Ng, Fremont, CA (US);
Matthew N. Papakipos, Menlo Park, CA (US);
Jason R. Redgrave, Mountain View, CA (US);
Sushma S. Trivedi, Sunnyvale, CA (US);
Nathan D. Tuck, San Diego, CA (US);
Shun Wai Go, Milpitas, CA (US);
Lindy Fung, Sunnyvale, CA (US);
Tuan D. Nguyen, San Jose, CA (US);
Joseph P. Grass, Menlo Park, CA (US);
Bo Hong, San Jose, CA (US);
Abraham Mammen, Pleasanton, CA (US);
Abbas Rashid, Fremont, CA (US);
Albert Suan-Wei Tsay, Fremont, CA (US);
Apple Computer, Inc., Cupertino, CA (US);
Abstract
A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.