The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2007

Filed:

Jun. 21, 2004
Applicants:

Weon-ho Park, Suwon-si, KR;

Hyun-khe Yoo, Suwon-si, KR;

Inventors:

Weon-Ho Park, Suwon-si, KR;

Hyun-Khe Yoo, Suwon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The memory transistor positions on the semiconductor substrate and comprises a gate insulating film formed on the semiconductor substrate and a memory transistor gate formed on the gate insulating film. The gate insulating film includes a tunnel insulating film. The select transistor positions on the semiconductor substrate and is separated from the memory transistor gate. The select transistor comprises a gate insulating film formed on the semiconductor substrate and a select transistor gate formed on the gate insulating film. A floating junction region is formed of a second conductive type on the semiconductor substrate below the tunnel insulating film. The common source region of a second conductive type is formed on the semiconductor substrate adjacent to the memory transistor gate and separated from the floating junction region. A bit line junction region of a second conductive type is formed on the semiconductor substrate adjacent to the select transistor gate and is separated from the floating junction region, wherein the common source region includes a single junction region with a first doping concentration, and a depth of the common source region is shallower than a depth of the floating junction region and the bit line junction region.


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