The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7164763 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 16, 2007

Filed:

Jun. 30, 2004
Applicants:

Scott A. George, Walnut Creek, CA (US);

Marius Goldenberg, Austin, TX (US);

Richard D. Loveman, Buda, TX (US);

Carlos A. Laiz, Austin, TX (US);

Inventors:

Scott A. George, Walnut Creek, CA (US);

Marius Goldenberg, Austin, TX (US);

Richard D. Loveman, Buda, TX (US);

Carlos A. Laiz, Austin, TX (US);

Assignee:

Silicon Laboratories, Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04M 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A power offload network has a node for receiving at least one supply V. The power offload network includes at least one switch and a power offload element providing a supply drop of VR. The switch is configurable for selecting a linefeed supply level from the set including {V, V−VR}. A subscriber line interface circuit receives the selected linefeed supply level for driving a subscriber line.


Find Patent Forward Citations

George, Scott. (2007). Power offloading for a subscriber line interface circuit (U.S. Patent No. 7164763). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7164763

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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