Vertical memory cell and manufacturing method thereof

Abstract

A vertical split gate memory cell of silicon-oxide-nitride-oxide-silicon (SONOS) type formed in a trench of a semiconductor substrate includes a first doping region, a second doping region, a conductive line, a conductive plug, a first insulating layer and a second insulating layer, wherein the conductive line and conductive plug serve as a select gate and a control gate of the vertical split gate memory cell, respectively. The first doping region of a first conductive type is underneath the bottom of the trench, whereas the second doping region of the first conductive type is beside the top of the trench. The conductive line serving as the select gate is formed in the bottom of the trench and in operation relation to the first doping region. The first insulating layer is between the conductive line and the first doping region for insulation. The conductive plug is formed above the conductive line, and insulated from the conductive line by the second insulating layer. As to the formation of isolating plugs, for example, composed of CVD oxide, between memory cells, it can be done by etching conductive lines into holes and filling up the holes with CVD oxide or by filling the trenches with oxide between memory cells first.