Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing

Abstract

An integrated circuit device utilizes a serial scan chain register to support efficient reliability testing of internal circuitry that is not readily accessible from the I/O pins of the device. The scan chain register has scan chain latch units that support a toggle mode of operation. The scan chain register is provided with serial and parallel input ports and serial and parallel output ports. Each of the plurality of scan chain latch units includes a latch element and additional circuit elements that are configured to selectively establish a feedback path in the respective latch unit. This feedback path operates to pass an inversion of a signal at an output of the latch to an input of the latch when the corresponding scan chain latch unit is enabled to support a toggle mode of operation.