The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2007

Filed:

Mar. 08, 2005
Applicants:

Avinash Kallat, Marlborough, MA (US);

John Phinney, Westford, MA (US);

Amnon Izhar, Brookline, MA (US);

Inventors:

Avinash Kallat, Marlborough, MA (US);

John Phinney, Westford, MA (US);

Amnon Izhar, Brookline, MA (US);

Assignee:

EMC Corporation, Hopkinton, MA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

An interrupt controller enables multiple CPUs to control access to an increased number of interrupts. Each of a plurality of CPUs is able to block interrupts written to the interrupt controller at multiple levels. First, each CPU is able to block interrupts at the interrupt level. In other words, a CPU is able to block one or more individual interrupt requests from I/O devices from being sent to that CPU. Second, each CPU is able to block interrupts from one or more entire MSI interrupt registers from being sent to that CPU. The interrupt controller is fully programmable by the CPUs in software and thus is very flexible, as the priority of interrupts can be controlled by the CPUs according to the requirements of the CPUs based on the various operational demands of the CPUs. Any of 512 possible interrupt requests are capable of being routed to any particular one CPU, any combination of the CPUs or to all of the CPUs.


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