The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2007
Filed:
May. 27, 2005
Wayson J. Lowe, Belmont, CA (US);
Eunice Y. D. Hao, Saratoga, CA (US);
Tony K. Ngai, Saratoga, CA (US);
Peter H. Alfke, Los Altos Hills, CA (US);
Wayson J. Lowe, Belmont, CA (US);
Eunice Y. D. Hao, Saratoga, CA (US);
Tony K. Ngai, Saratoga, CA (US);
Peter H. Alfke, Los Altos Hills, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
An integrated circuit having an embedded first-in, first-out ('FIFO') memory system uses an embedded block random access memory ('BRAM'). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.