The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7160177 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 09, 2007

Filed:

Jan. 23, 2004
Applicants:

Volker Herold, Jena, DE;

Christian-toralf Weber, Magdeburg, DE;

Juergen Weiser, Magedeburg, DE;

Inventors:

Volker Herold, Jena, DE;

Christian-Toralf Weber, Magdeburg, DE;

Juergen Weiser, Magedeburg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B24B 49/00 (2006.01); B24B 51/00 (2006.01); B24B 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A device for high-precision machining of the surface of an object, such as for polishing and lapping semiconductor substrates, in which the object is held on an accommodation surface for its machining. The accommodation surface can be deformed by means of a actuators connected to the surface in a positive-lock and/or non-positive-lock manner. The actuators are provided between a base plate and an accommodation plate that are mechanically biased relative to one another. The accommodation plate is configured, on its inside, with concentric grooves forming rigid rings in the axial direction. The individual rings are connected by solid substance joints. Piezo-stacks configured as actuator-sensor elements, as well as springs, are disposed between the faces of the rings and the base plates and are offset relative to one another by 120°.


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Herold, Volker. (2007). Method and device for the high-precision machining of the surface of an object, especially for polishing and lapping semiconductor substrates (U.S. Patent No. 7160177). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7160177

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